View PD442000L-X_1756883.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1997 mos integrated circuit m m m m PD442000L-X 2m-bit cmos static ram 256k-word by 8-bit extended temperature operation data sheet document no. m12509ej6v0ds00 (6th edition) date published august 1998 ns cp (k) printed in japan the information in this document is subject to change without notice. the mark h shows major revised points. description the m PD442000L-X is a high speed, low power, 2,097,152 bits (262,144 words by 8 bits) cmos static ram. the m PD442000L-X has two chip enable pins (/ce1, ce2) to extend the capacity. and battery backup is available. b, c and d versions are low voltage versions. the m PD442000L-X is packed in 32-pin plastic tsop (i) and 36-pin plastic fpbga. features 262,144 words by 8 bits organization fast access time : 70, 85,100,120,150,180, 250 ns (max.) low voltage operation (b version: v cc = 2.7 to 3.6 v, c version: v cc = 2.2 to 3.6 v, d version: v cc = 1.8 to 3.6 v) operating ambient temperature (x version: t a = C25 to +85 c) 1.5 v (min.) data retention output enable input for easy application two chip enable inputs: /ce1, ce2 part number access time operating supply operating ambient supply current ns (max.) voltage v temperature c at operating ma (max.) at standby m a (max.) at data retention m a (max.) m pd442000l-bxxx 70 note , 85, 100 2.7 to 3.6 - 25 to +85 35 2 2 m pd442000l-cxxx 100, 120, 150 2.2 to 3.6 30 m pd442000l-dxxx 150, 180, 250 1.8 to 3.6 25 note under development
2 m m m m PD442000L-X ordering information (1/2) part number package access time ns (max.) operating supply voltage v operating temperature c remark m pd442000lgu-b70x-9jh note 32-pin plastic tsop (i) 70 2.7 to 3.6 - 25 to +85 b version m pd442000lgu-b85x-9jh (8 13.4 mm) (normal bent) 85 m pd442000lgu-b10x-9jh 100 m pd442000lgu-b70x-9kh note 32-pin plastic tsop (i) 70 m pd442000lgu-b85x-9kh (8 13.4 mm) (reverse bent) 85 m pd442000lgu-b10x-9kh 100 m pd442000lgz-b70x-kjh note 32-pin plastic tsop (i) 70 m pd442000lgz-b85x-kjh (8 20.0 mm) (normal bent) 85 m pd442000lgz-b10x-kjh 100 m pd442000lgz-b70x-kkh note 32-pin plastic tsop (i) 70 m pd442000lgz-b85x-kkh (8 20.0 mm) (reverse bent) 85 m pd442000lgz-b10x-kkh 100 m pd442000lf1-bs1-b70x note 36-pin plastic fpbga 70 m pd442000lf1-bs1-b85x note (6.5 10.5 mm) 85 m pd442000lf1-bs1-b10x note 100 m pd442000lgu-c10x-9jh 32-pin plastic tsop (i) 100 2.2 to 3.6 - 25 to +85 c version m pd442000lgu-c12x-9jh (8 13.4 mm) (normal bent) 120 m pd442000lgu-c15x-9jh 150 m pd442000lgu-c10x-9kh 32-pin plastic tsop (i) 100 m pd442000lgu-c12x-9kh (8 13.4 mm) (reverse bent) 120 m pd442000lgu-c15x-9kh 150 m pd442000lgz-c10x-kjh 32-pin plastic tsop (i) 100 m pd442000lgz-c12x-kjh (8 20.0 mm) (normal bent) 120 m pd442000lgz-c15x-kjh 150 m pd442000lgz-c10x-kkh 32-pin plastic tsop (i) 100 m pd442000lgz-c12x-kkh (8 20.0 mm) (reverse bent) 120 m pd442000lgz-c15x-kkh 150 m pd442000lf1-bs1-c10x note 36-pin plastic fpbga 100 m pd442000lf1-bs1-c12x note (6.5 10.5 mm) 120 m pd442000lf1-bs1-c15x note 150 note under development
3 m m m m PD442000L-X ordering information (2/2) part number package access time ns (max.) operating supply voltage v operating temperature c remark m pd442000lgu-d15x-9jh 32-pin plastic tsop (i) 150 1.8 to 3.6 - 25 to +85 d version m pd442000lgu-d18x-9jh (8 13.4 mm) (normal bent) 180 m pd442000lgu-d25x-9jh 250 m pd442000lgu-d15x-9kh 32-pin plastic tsop (i) 150 m pd442000lgu-d18x-9kh (8 13.4 mm) (reverse bent) 180 m pd442000lgu-d25x-9kh 250 m pd442000lgz-d15x-kjh 32-pin plastic tsop (i) 150 m pd442000lgz-d18x-kjh (8 20.0 mm) (normal bent) 180 m pd442000lgz-d25x-kjh 250 m pd442000lgz-d15x-kkh 32-pin plastic tsop (i) 150 m pd442000lgz-d18x-kkh (8 20.0 mm) (reverse bent) 180 m pd442000lgz-d25x-kkh 250 m pd442000lf1-bs1-d15x note 36-pin plastic fpbga 150 m pd442000lf1-bs1-d18x note (6.5 10.5 mm) 180 m pd442000lf1-bs1-d25x note 250 note under development
4 m m m m PD442000L-X pin configuration (marking side) /xxx indicates active low signal. 32-pin plastic tsop (i) (8 13.4 mm) (normal bent) [ m m m m pd442000lgu-bxxx-9jh ] [ m m m m pd442000lgu-cxxx-9jh ] [ m m m m pd442000lgu-dxxx-9jh ] a11 a9 a8 a13 /we ce2 a15 v cc a17 a16 a14 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 a0 - a17 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground
5 m m m m PD442000L-X 32-pin plastic tsop (i) (8 13.4 mm) (reverse bent) [ m m m m pd442000lgu-bxxx-9kh ] [ m m m m pd442000lgu-cxxx-9kh ] [ m m m m pd442000lgu-dxxx-9kh ] /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 /we ce2 a15 v cc a17 a16 a14 a12 a7 a6 a5 a4 a0 - a17 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground
6 m m m m PD442000L-X 32-pin plastic tsop (i) (8 20.0 mm) (normal bent) [ m m m m pd442000lgz-bxxx-kjh ] [ m m m m pd442000lgz-cxxx-kjh ] [ m m m m pd442000lgz-dxxx-kjh ] a11 a9 a8 a13 /we ce2 a15 v cc a17 a16 a14 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 a0 - a17 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground
7 m m m m PD442000L-X 32-pin plastic tsop (i) (8 20.0 mm) (reverse bent) [ m m m m pd442000lgz-bxxx-kkh ] [ m m m m pd442000lgz-cxxx-kkh ] [ m m m m pd442000lgz-dxxx-kkh ] /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 /we ce2 a15 v cc a17 a16 a14 a12 a7 a6 a5 a4 a0 - a17 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground
8 m m m m PD442000L-X 36-pin plastic fpbga (6.5 10.5 mm) [ m m m m pd442000lf1-bs1-bxxx ] [ m m m m pd442000lf1-bs1-cxxx ] [ m m m m pd442000lf1-bs1-dxxx ] 1 2 3 4 5 6 d f e b c a 6 5 4 3 2 1 bottom view top view nec 654321 pin no. func. pin no. func. pin no. func. pin no. func. pin no. func. pin no. func a a6 a12 a5 a14 a4 a17 a3 v cc a2 ce2 a1 a13 bb6a6b5a7b4a16b3a15b2/web1a8 cc6a4c5a5c4 ic c3 ic c2a11c1a9 dd6a3d5a2d4 ic d3 ic d2a10d1/oe e e6 a1 e5 i/o2 e4 i/o3 e3 i/o4 e2 i/o6 e1 /ce1 f f6 a0 f5 i/o1 f4 gnd f3 i/o5 f2 i/o7 f1 i/o8 a0 - a17 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground ic note : internal connection note leave this pin unconnected or connect to gnd.
9 m m m m PD442000L-X block diagram address buffer row decoder memory cell array 2,097,152 bits input data controller a0 a17 i/o1 i/o8 sense/switch column decoder output data controller address buffer /ce1 ce2 /oe /we v cc gnd truth table /ce1 ce2 /oe /we mode i/o supply current h not selected high impedance i sb l l h h h output disable i cca l h l h read d out lh lwrite d in remark : dont care
10 m m m m PD442000L-X electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc C0.5 note to +4.6 v input / output voltage v t C0.5 note to v cc +0.5 v operating ambient temperature t a C25 to +85 c storage temperature t stg C55 to +125 c note C3.0 v (min.) (pulse width : 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol conditions m pd442000l-bxxx m pd442000l-cxxx m pd442000l-dxxx unit min. max. min. max. min. max. supply voltage v cc 2.7 3.6 2.2 3.6 1.8 3.6 v high level input voltage v ih 2.7 v v cc 3.6 v 2.4 v cc +0.5 2.4 v cc +0.5 2.4 v cc +0.5 v 2.2 v v cc < 2.7 v C C 2.0 v cc +0.5 2.0 v cc +0.5 1.8 v v cc < 2.2 vCCCC1.6v cc +0.5 low level input voltage v il C0.3 note +0.5 C0.3 note +0.3 C0.3 note +0.2 v operating ambient temperature t a C25 +85 C25 +85 C25 +85 c note C1.5 v (min.) (pulse width : 30 ns)
11 m m m m PD442000L-X dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition m pd442000l-bxxx m pd442000l-cxxx m pd442000l-dxxx unit min. typ. max. min. typ. max. min. typ. max. input leakage i li v in = 0 v to v cc C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a current i/o leakage i lo v i/o = 0 v to v cc , /ce1 = v ih or C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a current ce2 = v il or /we = v il or /oe = v ih operating i cca1 /ce1 = v il , ce2 = v ih , 303525302025ma supply current i i/o = 0 ma, v cc 2.7 C C 20 25 15 20 minimum cycle time v cc 2.2 C C C C 10 15 i cca2 /ce1 = v il , ce2 = v ih ,101010 i i/o = 0 ma v cc 2.7 C 8 8 v cc 2.2 C C 5 i cca3 /ce1 0.2 v, ce2 3 v cc C 0.2 v, 8 8 8 cycle = 1 mhz, i i/o = 0 ma, v il 0.2 v, v cc 2.7 C 6 6 v ih 3 v cc C 0.2 v v cc 2.2 C C 5 standby i sb /ce1 = v ih or ce2 = v il 0.3 0.3 0.3 ma supply current i sb1 /ce1 3 v cc C 0.2 v, 0.1 2 0.1 2 0.1 2 m a ce2 3 v cc C 0.2 v v cc 2.7 C C 0.08 2 0.08 2 v cc 2.2 C C C C 0.05 1.5 i sb2 ce2 0.2 v 0.1 2 0.1 2 0.1 2 v cc 2.7 C C 0.08 2 0.08 2 v cc 2.2 C C C C 0.05 1.5 high level v oh i oh = C0.5 ma 2.4 2.4 2.4 v output voltage v cc 2.7 C 1.8 1.8 v cc 2.2 C C 1.5 low level v ol i ol = 1.0 ma 0.4 0.4 0.4 v output voltage remarks 1. v in : input voltage 2. these dc characteristics are in common regardless of package types and access time. capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage 2. these parameters are periodically sampled and not 100% tested.
12 m m m m PD442000L-X ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions m m m m pd442000l-b70x, 442000l-b85x, 442000l-b10x input waveform (rise and fall time 5 ns) test points 0.5 v 2.4 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load 1ttl + 50pf m m m m pd442000l-c10x, 442000l-c12x, 442000l-c15x input waveform (rise and fall time 5 ns) output waveform test points 1.1 v 1.1 v output load 1ttl + 50pf h test points 0.3 v 2.0 v 1.1 v 1.1 v
13 m m m m PD442000L-X m m m m pd442000l-d15x, 442000l-d18x, 442000l-d25x input waveform (rise and fall time 5 ns) test points 0.2 v 1.6 v 0.9 v 0.9 v output waveform test points 0.9 v 0.9 v output load 1ttl + 50pf
14 m m m m PD442000L-X read cycle (b version) parameter symbol - b70x - b85x - b10x unit conditions min. max. min. max. min. max. read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns note1 /ce1 access time t co1 70 85 100 ns ce2 access time t co2 70 85 100 ns /oe to output valid t oe 35 40 50 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns note2 ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 555ns /ce1 to output in high impedance t hz1 25 30 35 ns ce2 to output in high impedance t hz2 25 30 35 ns /oe to output hold in high impedance t ohz 25 30 35 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. read cycle (c version) parameter symbol - c10x - c12x - c15x unit conditions min. max. min. max. min. max. read cycle time t rc 100 120 150 ns address access time t aa 100 120 150 ns note1 /ce1 access time t co1 100 120 150 ns ce2 access time t co2 100 120 150 ns /oe to output valid t oe 50 60 70 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns note2 ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 555ns /ce1 to output in high impedance t hz1 35 40 45 ns ce2 to output in high impedance t hz2 35 40 45 ns /oe to output hold in high impedance t ohz 35 40 45 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
15 m m m m PD442000L-X read cycle (d version) parameter symbol - d15x - d18x - d25x unit conditions min. max. min. max. min. max. read cycle time t rc 150 180 250 ns address access time t aa 150 180 250 ns note1 /ce1 access time t co1 150 180 250 ns ce2 access time t co2 150 180 250 ns /oe to output valid t oe 70 80 100 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns note2 ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 555ns /ce1 to output in high impedance t hz1 45 50 60 ns ce2 to output in high impedance t hz2 45 50 60 ns /oe to output hold in high impedance t ohz 45 50 60 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. read cycle timing chart t hz2 t rc t oh t hz1 t olz t oe t lz2 t co2 t lz1 t co1 t ohz t aa high impedance data out /oe (input) ce2 (input) /ce1 (input) address (input) i/o (output) remark in read cycle, /we should be fixed to high level.
16 m m m m PD442000L-X write cycle (b version) parameter symbol - b70x - b85x - b10x unit condition min. max. min. max. min. max. write cycle time t wc 70 85 100 ns /ce1 to end of write t cw1 55 70 80 ns ce2 to end of write t cw2 55 70 80 ns address valid to end of write t aw 55 70 80 ns address setup time t as 000ns write pulse width t wp 50 60 60 ns write recovery time t wr 000ns data valid to end of write t dw 30 35 40 ns data hold time t dh 000ns /we to output in high impedance t whz 25 30 35 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. write cycle (c version) parameter symbol - c10x - c12x - c15x unit condition min. max. min. max. min. max. write cycle time t wc 100 120 150 ns /ce1 to end of write t cw1 80 100 120 ns ce2 to end of write t cw2 80 100 120 ns address valid to end of write t aw 80 100 120 ns address setup time t as 000ns write pulse width t wp 60 80 100 ns write recovery time t wr 000ns data valid to end of write t dw 40 50 60 ns data hold time t dh 000ns /we to output in high impedance t whz 35 40 50 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
17 m m m m PD442000L-X write cycle (d version) parameter symbol - d15x - d18x - d25x unit condition min. max. min. max. min. max. write cycle time t wc 150 180 250 ns /ce1 to end of write t cw1 120 150 200 ns ce2 to end of write t cw2 120 150 200 ns address valid to end of write t aw 120 150 200 ns address setup time t as 000ns write pulse width t wp 100 120 160 ns write recovery time t wr 000ns data valid to end of write t dw 60 75 100 ns data hold time t dh 000ns /we to output in high impedance t whz 50 60 80 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
18 m m m m PD442000L-X write cycle timing chart 1 (/we controlled) t wc t cw1 t aw t wp t as t wr t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address(input) /ce1 (input) /we (input) i/o (input/output) ce2 (input) t cw2 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remarks 1. write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2. 2. if /ce1 changes to low level at the same time or after the change of /we to low level, or if ce2 changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance.
19 m m m m PD442000L-X write cycle timing chart 2 (/ce1 controlled) t wc t as t cw1 t aw t wp t wr t dw t dh data in high impedance address (input) /ce1 (input) /we (input) i/o (input) high impedance ce2 (input) t cw2 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2.
20 m m m m PD442000L-X write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t aw t wp t wr t dw t dh data in high impedance address (input) ce2 (input) /we (input) i/o (input) high impedance /ce1 (input) t cw1 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2.
21 m m m m PD442000L-X low v cc data retention characteristics parameter symbol test conditions min. typ. max. unit data retention supply voltage v ccdr1 /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2v 1.5 3.6 v v ccdr2 ce2 0.2 v 1.5 3.6 data retention supply current i ccdr1 v cc = 3.0 v, /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v or ce2 0.2 v 0.1 2 m a i ccdr2 v cc = 3.0 v, ce2 0.2 v 0.1 2 chip deselection to data retention mode t cdr 0ns operation recovery time t r t rc note ns note t rc : read cycle time.
22 m m m m PD442000L-X data retention timing chart (1) /ce1 controlled t cdr data retention mode v ih (min. ) v ccdr (min. ) v il (max. ) t r v cc /ce1 /ce1 3 v cc C 0.2 v gnd 3.0 v note v cc (min. ) note b version : 2.7 v, c version : 2.2 v, d version : 1.8 v remark on the data retention mode by controlling /ce1, the input level of ce2 must be ce2 3 v cc - 0.2 v or ce2 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state. (2) ce2 controlled t cdr data retention mode 3.0 v v ih (min. ) v ccdr (min. ) v il (max. ) t r v cc ce2 ce2 0.2 v gnd note v cc (min. ) note b version : 2.7 v, c version : 2.2 v, d version : 1.8 v remark the other pins (/ce1, address, i/o, /we, /oe) can be in high impedance state.
23 m m m m PD442000L-X package drawings 32pin plastic tsop ( i ) (8x13.4) note (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. item millimeters inches p32gu-50-9jh-1 b 0.45 max. 0.018 max. c 0.5 (t.p.) 0.020 (t.p.) detail of lead end a 8.0?.1 0.315?.004 h 12.4?.2 0.488?.008 b t n d 0.22?.05 0.009 +0.002 ?.003 g 1.0?.05 0.039 +0.003 ?.009 i 11.8?.1 0.465 +0.004 ?.005 j 0.8?.2 0.031 +0.009 ?.008 k l 0.5 0.020 m 0.08 0.003 n 0.08 0.003 q 0.1?.05 0.004?.002 p 13.4?.2 0.528 +0.008 ?.009 s 1.2 max. 0.048 max. r3 3 t 0.25 0.010 u 0.6?.15 0.024 +0.006 ?.007 +5 ? +5 ? (2) "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.331 inch max.>) m u l r q s d m c g k j 1 16 32 17 a 0.145 +0.025 ?.015 0.006?.001 h p i
24 m m m m PD442000L-X 32pin plastic tsop ( i ) (8x13.4) note (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. item millimeters inches p32gu-50-9kh-1 b 0.45 max. 0.018 max. c 0.5 (t.p.) 0.020 (t.p.) detail of lead end a 8.0?.1 0.315?.004 h 12.4?.2 0.488?.008 b t n d 0.22?.05 0.009 +0.002 ?.003 g 1.0?.05 0.039 +0.003 ?.009 i 11.8?.1 0.465 +0.004 ?.005 j 0.8?.2 0.031 +0.009 ?.008 k l 0.5 0.020 m 0.08 0.003 n 0.08 0.003 q 0.1?.05 0.004?.002 p 13.4?.2 0.528 +0.008 ?.009 s 1.2 max. 0.048 max. r3 3 t 0.25 0.010 u 0.6?.15 0.024 +0.006 ?.007 +5 ? +5 ? (2) "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.331 inch max.>) 1 16 32 17 m u l r q s d m c g a k j h p i 0.145 +0.025 ?.015 0.006?.001
25 m m m m PD442000L-X notes 32 pin plastic tsop ( i ) (8 20) item millimeters inches a b c e i 8.00.1 0.5 (t.p.) 0.10.05 0.45 max. k 1.2 max. 18.40.1 0.1450.05 f 0.10 m 0.3150.004 0.018 max. 0.0040.002 0.724 0.006 0.048 max. 0.004 0.020 (t.p.) d 0.220.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.327 inch max.>) c r d m m l +0.002 C0.003 0.970.08 g 0.038 +0.004 C0.003 +0.005 C0.004 l 0.5 0.020 0.10 n 0.004 p 20.00.2 0.787 +0.009 C0.008 q3 3 +5 C3 +5 C3 0.25 r 0.010 s32gz-50-kjh1 s 0.600.15 0.024 +0.006 C0.007 +0.002 C0.003 j 0.80.2 0.031 +0.009 C0.008 1 16 32 17 s p g f e s q n k i b detail of lead end j a s 1. controlling dimension millimeter.
26 m m m m PD442000L-X notes 32 pin plastic tsop ( i ) (8 20) item millimeters inches a b c e i 8.00.1 0.5 (t.p.) 0.10.05 0.45 max. k 1.2 max. 18.40.1 0.1450.05 f 0.10 m 0.3150.004 0.018 max. 0.0040.002 0.724 0.006 0.048 max. 0.004 0.020 (t.p.) d 0.220.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.327 inch max.>). c r d m m g +0.002 C0.003 0.970.08 g 0.038 +0.004 C0.003 +0.005 C0.004 l 0.5 0.020 0.10 n 0.004 p 20.00.2 0.787 +0.009 C0.008 q3 3 +5 C3 +5 C3 0.25 r 0.010 s32gz-50-kkh1 s 0.600.15 0.024 +0.006 C0.007 +0.002 C0.003 j 0.80.2 0.031 +0.009 C0.008 1 16 32 17 s n b a f e q s l k i p j detail of lead end s 1. controlling dimension millimeter.
27 m m m m PD442000L-X 36 pin plastic-fpbga (6.5 10.5) item millimeters b c 0.71 6.5 d 0.32 a 10.5 e f 0.75 1.03 h i 1.375 0.45 g 3.375 b a f f h i f g e e d c c d
28 m m m m PD442000L-X recommended soldering conditions please consult with our sales offices for soldering conditions of the m PD442000L-X. type of surface mount device m pd442000lgu-bx-9jh: 32-pin plastic tsop (i) (8 13.4 mm) (normal bent) m pd442000lgu-cx-9jh: 32-pin plastic tsop (i) (8 13.4 mm) (normal bent) m pd442000lgu-dx-9jh: 32-pin plastic tsop (i) (8 13.4 mm) (normal bent) m pd442000lgu-bx-9kh: 32-pin plastic tsop (i) (8 13.4 mm) (reverse bent) m pd442000lgu-cx-9kh: 32-pin plastic tsop (i) (8 13.4 mm) (reverse bent) m pd442000lgu-dx-9kh: 32-pin plastic tsop (i) (8 13.4 mm) (reverse bent) m pd442000lgz-bx-kjh: 32-pin plastic tsop (i) (8 20.0 mm) (normal bent) m pd442000lgz-cx-kjh: 32-pin plastic tsop (i) (8 20.0 mm) (normal bent) m pd442000lgz-dx-kjh: 32-pin plastic tsop (i) (8 20.0 mm) (normal bent) m pd442000lgz-bx-kkh: 32-pin plastic tsop (i) (8 20.0 mm) (reverse bent) m pd442000lgz-cx-kkh: 32-pin plastic tsop (i) (8 20.0 mm) (reverse bent) m pd442000lgz-dx-kkh: 32-pin plastic tsop (i) (8 20.0 mm) (reverse bent) m pd442000lf1-bs1-bx: 36-pin plastic fpbga (6.5 10.5 mm) m pd442000lf1-bs1-cx: 36-pin plastic fpbga (6.5 10.5 mm) m pd442000lf1-bs1-dx: 36-pin plastic fpbga (6.5 10.5 mm)
29 m m m m PD442000L-X [memo]
30 m m m m PD442000L-X [memo]
31 m m m m PD442000L-X 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme-diately after power-on for devices having reset function. notes for cmos devices
m m m m PD442000L-X [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

▲Up To Search▲

Price & Availability of PD442000L-X

	To Download PD442000L-X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .